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ir3092pbf page 1 of 37 09/07/05 data sheet 2 phase opteron, athlon, or vr10.x control ic description the ir3092 control ic provides a full featured, sin gle chip solution to implement robust power convers ion solutions for three different microprocessor famili es; 1) amd opteron, 2) amd athlon or 3) intel vr10. x family of processors. the user can select the appr opriate vid range with a single pin. pwm control a nd 2 phase gate drive functions are integrated into a si ngle ic. in addition to cpu power, the ir3092 offer s a compact, efficient solution for high current pol co nverters. features x 5 bit or 6 bit vid with 0.5% overall system accura cy x selectable vid code for amd opteron, amd athlon or intel vr10.x x programmable slew rate response to on-the-fly vi d code changes x 3.5a gate drive capability x programmable 100khz to 540khz oscillator x programmable voltage positioning (can be disabled) x programmable softstart x programmable hiccup over-current protection with d elay to prevent false triggering x simplified powergood provides indication of proper operation and avoids false triggering x operates up to 21v input with 7.8v under-voltage l ockout x 5v uvl with 4.3v under-voltage lockout threshold x adjustable voltage, 150ma bias regulator provides mosfet drive voltage x enable input x ovp output x available in a 48l mlpq package ordering information device order quantity ir3092mtrpbf 3000 per reel IR3092MPBF 100 piece strips x package information 48l mlpq (7 x 7 mm body) ja = 27 o c/w scomp ocset nc setbias 48ld mlpq nc pwrgd nc gat el2 vdac vid0 enable vccl gat eh2 nc vid3 fb csinp2 nc vosns- vid_sel nc ovp biasout nc vid1 vcch1 nc rosc ss/del lgnd nc vdrp 5vuvl pgnd2 gat el1 gat eh1 eaout vid2 nc csinp1 ir3092 vid5 nc csinm vcch2 vid4 vcc pgnd1 nc downloaded from: http:///
ir3092pbf page 2 of 37 09/07/05 pin description pin# pin symbol pin description 1 vid3 inputs to vid d to a converter 2 vid4 inputs to vid d to a converter 3 rosc connect a resistor to vosns- to program osci llator frequency and fb, ocset, bbfb, and vdac bias currents 4 vosns- remote sense input. connect to ground at t he load. 5 ocset programs the hiccup over-current threshold through an external resistor tied to vdac and an internal c urrent source. 6 vdac regulated voltage programmed by the vid inputs. cur rent sensing and over current protection are refere nced to this pin. connect an external rc network to vosn s- to program dynamic vid slew rate. 7 vdrp buffered iin signal. connect an external rc network to fb to program converter output impedance 8 fb inverting input to the error amplifier. converter o utput voltage is offset from the vdac voltage throu gh an external resistor connected to the converter output voltage at the load and an internal current source . bias current is a function of rosc. also ovpsense. 9 eaout output of the error amplifier 10 ss/del controls converter softstart, power good, and over- current timing. connect an external capacitor to lg nd to program the timing. 11 scomp compensation for the current share control loop. c onnect a capacitor to ground to set the control loo ps bandwidth. phase 2 is forced to match phase 1s cu rrent. 12 n/c no connect. 13 lgnd local ground and ic substrate connection 14 setbias external resistor to ground sets voltage at biasout pin. bias current is a function of ros c. 15 vcc power for internal circuitry and source for biasout regulator 16-17 n/c no connect. 18 biasout 150ma open-looped regulated voltage set by setbias for gate drive bias. 19 pwrgd open collector output that drives low duri ng softstart or any fault condition. connect extern al pull-up. 20 csinp2 non-inverting input to the phase 2 curren t sense amplifier. 21 n/c no connect. 22 vid_sel ground selects vr10 vid, float selects o pteron vid, vcc selects athlon vid 23-27 n/c no connect. 28 vcch2 power for phase 2 high-side gate driver 29 gateh2 phase 2 high-side gate driver output and input to gatel2 non-overlap comparator. 30 pgnd2 return for phase 2 gate drivers 31 gatel2 phase 2 low-side gate driver output and i nput to gateh2 non-overlap comparator. 32 5vuvl can be used to monitor the driver supply voltage or 5v supply voltage when converting from 5v. an und er voltage condition initiates soft start. 33 vccl power for phase 1 and 2 low-side gate drive rs. 34 gatel1 phase 1 low-side gate driver output and i nput to gateh1 non-overlap comparator. 35 pgnd1 return for phase 1 gate drivers 36 gateh1 phase 1 high-side gate driver output and input to gatel1 non-overlap comparator. 37 vcch1 power for phase 1 high-side gate driver 38 nc not connected 39 csinm1 inverting input to the phase 1current sen se amplifier. 40 csinp1 non-inverting input to the current sense amplifier. 41 ovp output that drives high during an over-volta ge condition. 42 enable enable input. a logic low applied to this pin puts the ic into fault mode. 43-44 n/c no connect. 45 vid5 inputs to vid d to a converter 46 vid0 inputs to vid d to a converter 47 vid1 inputs to vid d to a converter 48 vid2 inputs to vid d to a converter downloaded from: http:///
ir3092pbf page 3 of 37 09/07/05 absolute maximum ratings operating junction temperature..150 o c storage temperature range.-65 o c to 150 o c pin name vmax vmin isource isink 1 vid3 30v -0.3v 1ma 1ma 2 vid4 30v -0.3v 1ma 1ma 3 rosc 30v -0.5v 1ma 1ma 4 vosns- 0.5v -0.5v 10ma 10ma 5 ocset 30v -0.3v 1ma 1ma 6 vdac 30v -0.3v 1ma 1ma 7 vdrp 30v -0.3v 5ma 5ma 8 fb 30v -0.3v 1ma 1ma 9 eaout 10v -0.3v 10ma 20ma 10 ss/del 30v -0.3v 1ma 1ma 11 scomp 30v -0.3v 5ma 5ma 12 n/c n/a n/a n/a n/a 13 lgnd n/a n/a 50ma 1ma 14 setbias 30v -0.3v 1ma 1ma 15 vcc 30v -0.3v 1ma 250ma 16 n/c n/a n/a n/a n/a 17 n/c n/a n/a n/a n/a 18 biasout 30v -0.3v 250ma 1ma 19 pwrgd 30v -0.3v 1ma 20ma 20 csinp2 30v -0.3v 250ma 1ma 21 n/c n/a n/a n/a n/a 22 vid_sel 30v -0.3v 1ma 1ma 23 n/c n/a n/a n/a n/a 24 n/c n/a n/a n/a n/a 25 n/c n/a n/a n/a n/a 26 n/c n/a n/a n/a n/a 27 n/c n/a n/a n/a n/a 28 vcch2 30v -0.3v n/a 3a for 100ns, 200ma dc 29 gateh2 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 30 pgnd2 0.3v -0.3v 3a for 100ns, 200ma dc n/a 31 gatel2 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 32 5vuvl 30v -0.3v 1ma 1ma 33 vccl 30v -0.3v n/a 3a for 100ns, 200ma dc 34 gatel1 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 35 pgnd1 0.3v -0.3v 3a for 100ns, 200ma dc n/a 36 gateh1 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 37 vcch1 30v -0.3v n/a 3a for 100ns, 200ma dc 38 n/c n/a n/a n/a n/a 39 csinm1 30v -0.3v 250ma 1ma 40 csinp1 30v -0.3v 250ma 1ma 41 ovp 30v -0.3v 1ma 1ma 42 enable 30v -0.3v 1ma 1ma 43 n/c n/a n/a n/a n/a 44 n/c n/a n/a n/a n/a 45 vid5 30v -0.3v 1ma 1ma 46 vid0 30v -0.3v 1ma 1ma 47 vid1 30v -0.3v 1ma 1ma 48 vid2 30v -0.3v 1ma 1ma downloaded from: http:///
ir3092pbf page 4 of 37 09/07/05 electrical specifications unless otherwise specified, these specifications ap ply over: 7.3v ? v cc ? 21v, 4v ? v ccl ? 14v, 4v ? v cchx ? 28v, c gatehx =3.3nf, c gatelx =6.8nf, 0 o c ? t j ? 125 o c parameter test condition min typ max unit vdac reference system set-point accuracy -0.3v ?92616 - ?9&rqqhfw)%wr eaout, measure v(eaout) C v(vosns-) deviation from table 1. applies to all vid codes. 0.5 % source current r rosc = 42k ?9'$& 2&6(7 56 62 71 p a sink current r rosc = 42k ?9'$& 2&6(7 50 58 67 p a vid input threshold, intel vid_sel=0, referenced to vosns- 0.4 0.6 0.8 v vid input threshold, amd vid_sel=float, referenced to vosns- 1.3 1.5 1.7 v vid_sel opteron threshold 1.0 1.2 1.4 v vid_sel athlon threshold 3.0 3.4 3.8 v vid_sel float voltage tracks athlon threshold 2.1 2 .6 3.2 v vid_sel pull-up resistance v(vid_sel)<2.1v 30 60 10 0 k ? vid_sel pull-down resistance v(vid_sel)>3.2v 60 190 375 k ? vid pull-up current vid0-5 = 1v 9 15 27 p a vid float voltage referenced to lgnd 4.5 4.9 5.2 v vid = 11111 fault blanking delay to pwrgd assertion 0.5 1.7 4.1 p s error amplifier input offset voltage connect fb to eaout, measure v(eaout)-v(vdac). from table 1. applies to all vid codes and -0.3v ? vosns- ?91rwh -5 -1 3 mv fb bias current r rosc = 42k ? 28 30.5 33 p a dc gain note 1 90 100 105 db gain-bandwidth product note 1 4 7 mhz slew rate note 1, 50mv fb signal 1.25 v/ p s source current 280 380 500 p a sink current .75 1.0 1.5 ma max voltage 4.5 4.9 5.3 v min voltage 90 150 mv vdrp buffer amplifier positioning offset voltage v(vdrp) C v(vdac) with csinmx=csinpx=0, note 1. -125 0 125 mv output voltage range 0.2 3.75 v source current 5 10 20 ma sink current 200 280 400 p a downloaded from: http:///
ir3092pbf page 5 of 37 09/07/05 parameter test condition min typ max unit oscillator switching frequency r rosc = 42k ? 160 200 240 khz phase1 to phase2 shift gateh1 rise to gateh2 rise 1 55 170 190 biasout regulator setbias bias current r rosc = 42k ? 105 115 125 p a set point accuracy v(setbias)-v(biasout) @ 100ma 0. 1 0.3 0.55 v biasout dropout voltage i(biasout)=100ma,threshold when v(setbias)-v(biasout)=0.45v 1.2 1.8 2.5 v biasout current limit 150 300 450 ma soft start and delay ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.8 1.3 1.8 v charge current 25 55 75 p a hiccup discharge current 2.5 5.5 7.5 p a oc discharge current 25 45 70 p a charge/discharge current ratio 9 10 11 p a/ p a charge voltage 3.8 4.0 4.2 v delay comparator threshold relative to charge volta ge 200 240 280 mv delay comparator hysteresis 15 30 45 mv discharge comparator threshold 200 260 350 mv over-current comparator input offset voltage v(ocset)-v(vdac), csin=csinp1=csinp2, note 1. -125 0 125 mv ocset bias current r rosc = 42k ? 28 30 33 p a max ocset set point 3.95 v under-voltage lockout vcc start threshold 7.2 7.8 8.3 v vcc stop threshold 6.7 7.3 7.8 v vcc hysteresis start C stop 450 500 750 mv 5vuvl start threshold 4.05 4.3 4.55 v 5vuvl stop threshold 3.92 4.125 4.33 v 5vuvl hysteresis start C stop 100 175 250 mv 5vuvl input resistance to lgnd 24 36 72 k ? pwrgd output output voltage i(pwrgd) = 4ma 150 300 mv leakage current v(pwrgd) = 5.5v 0 10 p a enable input threshold, intel vid_sel=0, referenced to vosns- 0. 4 0.6 0.8 v threshold, amd vid_sel=float, referenced to vosns- 1.3 1.5 1.7 v input resistance 7.5 15 20 k ? pull-up voltage 2.4 3.0 3.7 v downloaded from: http:///
ir3092pbf page 6 of 37 09/07/05 parameter test condition min typ max unit gate drivers gateh rise time vcchx = 12v, measure 2v to 9v transition time, note 1 11 40 ns gateh fall time vcchx = 12v, measure 9v to 2v transition time, note 1 11 40 ns gatel rise time vccl = 12v, measure 2v to 9v transi tion time, note 1 20 65 ns gatel fall time vccl = 12v, measure 9v to 2v transi tion time, note 1 20 65 ns high voltage (ac) measure vccl C gatelx or vcchx C gatehx, note 1 0 0.5v v low voltage (ac) measure gatelx or gatehx, note 1 0 0.5v v gatel low to gateh high delay vcchx = vccl = 12v, measure the time from gatelx falling to 2v to gatehx rising to 2v, note 1 20 35 60 ns gateh low to gatel high delay vcchx = vccl = 12v, measure the time from gatehx falling to 2v to gatelx rising to 2v, note 1 20 35 60 ns disable pull-down current gathx or gatelx=2v with v cc = 0v. measure gate pull-down current 20 35 50 p a pwm comparator propagation delay vcchx = vccl = 12v, measure the t ime from eaout fall crossing vdac to gatehx falling to 11v. (note 1) 100 150 ns common mode input range 4 v internal ramp start voltage 0.45 0.7 0.9 v internal ramp amplitude 40 57 75 mv / %dtc current sense amplifier csinp1&2 bias current -0.5 -0.2 0.1 p a csinm bias current -1 -0.4 0.2 p a input current offset ratio csinm/csinpx 0.7 1.7 2.6 p a/ p a average input offset voltage (vdrp-vdac)/gain withc sinx=0, note1 . -4 0 4 mv offset voltage mismatch monitor i(scomp) -8 0 8 mv gain at t j = 25 o c 22.0 23.5 25.0 v/v gain at t j = 125 o c 18.5 20.0 24.0 v/v gain mismatch -0.3 0 0.3 v/v differential input range -25 75 mv common mode input range 0 2.8 v downloaded from: http:///
ir3092pbf page 7 of 37 09/07/05 note 1: guaranteed by design, but not tested in productio n note 2: vdac output is trimmed to compensate for error amp input offsets errors parameter test condition min typ max unit share adjust error amplifier input offset voltage note 1 -5 0 5 mv max duty cycle adjust ratio duty cycle of gateh2 to gateh1 1.5 2 3 %/% min duty cycle adjust ratio duty cycle of gateh2 to gateh1 0.6 0.5 0.4 %/% transconductance note 1 100 200 300 p a/v scomp source/sink current 15 28 40 p a equal duty cycle comparator threshold 0.45 0.7 0.85 v duty cycle match at startup dtc gateh1 C dtc gateh 2 -5 0 5 % scomp precharge current v(ss/del)=0 250 420 600 p a 0% duty cycle comparator threshold voltage (internal ramp1 start voltage) C (0dc threshold) 100 150 200 mv propagation delay vccl = 12v. step eaout from .8v t o .3v and measure time to gatelx transition to < 11v. 200 320 ns body braking disable comparator threshold compare v(fb) to v(vdac) 50 80 110 mv ovp vr10 comparator threshold vid_sel=0v. compare to v (vdac) 120 145 180 mv amd comparator threshold float vid_sel. compare to v(vdac) 360 480 600 mv propagation delay vccl = 12v. v(eaout)=0v. step fb 460mv above v(vdac). measure time to gatelx transition to >1v. 200 300 ns source current 10 20 ma pull down resistance ovp to pgnd1 20 45 80 k ? high voltage i(ovp)=10ma, v(vcc)-v(ovp) .8 1.2 1.6 v general vcc supply current 23 29 34 ma vosns- current -0.3v ? vosns- ? 0.3v, all vid codes 2 3 4 ma vcchx supply current (12v) 3 5 7 ma vcchx supply current (28v) 5 7 9 ma vccl supply current 5 10 16 ma downloaded from: http:///
ir3092pbf page 8 of 37 09/07/05 typical operating characteristics i(fb) and i(ocset) currents vs. rosc 0 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 rosc in kohms ua i(fb) in ua i(ocset) in ua i(vdac) sink and source currents vs. rosc 0 20 40 60 80 100 120 140 160 180 10 20 30 40 50 60 70 80 90 100 rosc in kohms ua i(vdac) source current i(vdac) sink current oscillator frequency vs. rosc 0 50 100 150 200 250 300 350 400 450 500 550 10 20 30 40 50 60 70 80 90 100 rosc in kohms frequency in khz i(setbias) vs. rosc 0 50 100 150 200 250 300 10 20 30 40 50 60 70 80 90 100 rosc in kohms ua frequency and bias current accuracy vs. rosc (inclu des temperature) 0 1 2 3 4 5 6 10 20 30 40 50 60 70 80 90 100 rosc (kohm) +/-3 sigma variation (%) frequency fb bias ocset bias setbias peak gate drive current vs. load capacitance 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 3.5 6 8.5 11 13.5 16 18.5 21 c(gatex) in nf i(gatex) in amps i(rise) i(fall) c downloaded from: http:///
ir3092pbf page 9 of 37 09/07/05 typical operating characteristics error amplifier frequency response frequency 1.0hz 10hz 100hz 1.0khz 10khz 100khz 1.0mhz 10mhz 100mhz db(v(comp)) p(v(comp)) -100 0 100 -180 93db dc gain 88 phase margin 3.1mhz crossover downloaded from: http:///
ir3092pbf page 10 of 37 09/07/05 ir3092 theory of operation 7.8v start 7.3v stop 45u on vccl fast dac 18ua 5.5u 4.9v - + bb disable comparator 80mv iovp on 45k 1.9us blanking 0.7v biasout ss rosc ovp - ++ error_amp csinm rsff s q qb r csinp1 scomp vcch1 5vuvl gatel2 vid2 gatehi gatehi pgnd ol_out drive ol_in in irosc summer enable + - share adjust error amp 55u - + over current vid5 - + -+ equal duty cy cle comparator irosc - + x25 gatehi1 vid1 vcc -+ ovp comparator -+ x25 pgnd1 vosns- 0.7v -+ delay 0 to irosc*3/4 gateh2 ocset irosc fault latch s q r vdrp vid4 - + 0% duty cycle summer + - irosc dac buffer 4v 1.243 0.55v 240mv chrg, 210mv dischrg pgnd2 u18 -+ discharge comparator gatel1 fb rsff s q qb r setbias eaout -+ uvl lgnd vccl 10p 10p gatelo gatelo pgnd drive ol_in in ol_out gatehi gatehi pgnd ol_out drive ol_in in 4 x irosc gatelo gatelo pgnd drive ol_in in ol_out csinp2 + - + - 1.3v sof tstart_clamp set dominant reset dominant reset dominant -+ vid0 pwrgd vdac clk1 clk2 irosc oscillator -+ pwm comparator 60k 0.7v irosc/2 -+ pwm comparator vid3 0.26v irosc dac out vid0 vid1 vid2 vid3 vid4 vosns- vid5 f11111 opteron_dac athlon_dac vdac fb 15k 3v off dac defaults to vr10 with vid_sel grounded disable vcch2 amd=1.5v intel=0.6v vosns- 110k 1 -+ uvl 3.3v 5v amd=450mv intel=150mv vid_sel 4.300v start 4.125v stop - + 1.2v - + 3.4v vdac vdac h forces irosc/2 at ss<0.7v figure 1 ? ir3092 block diagram pwm operation the ir3092 is a fully integrated 2 phase interleave d pwm control ic which uses voltage mode control wi th trailing edge modulation. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. the pwm block diagram of the ir3092 is shown in fig ure 2. refer to figure 3. upon receiving a clock pulse, t he rsff is set, the internal pwm ramp voltage begin s to increase, the low side driver is turned off, and the high side dr iver is then turned on. for phase 1, an internal 1 0pf capacitor is charged by a current source thats proportional to the swit ching frequency resulting in a ramp rate of 57mv pe r percent duty cycle. for example, if the steady-state operating switch n ode duty cycle is 10%, then the internal ramp ampli tude is typically 570mv from the starting point (or floor) to the cro ssing of the eaout control voltage. when the pwm r amp voltage exceeds the error amplifiers output voltage, the r sff is reset. this turns off the high side driver, turns on the low side driver, and discharges the pwm ramp to 0.7v until t he next clock pulse. downloaded from: http:///
ir3092pbf page 11 of 37 09/07/05 csinm clk1 clk2 irosc u39 oscblock 10p 10p reset dominant rosc rosc vdrp buffer reset dominant -+ bb disable 80mv 0.55v irosc -+ pwm comparator 0 to irosc*3/4 + - share adjust error amp irosc - + error amplifier 0.7v rcs2 rsff s q qb r csc2 -+ irosc/2 ccs1 1 2 ccs2 -+ pwm comparator rsc2 rcs1 ccomp cdac vdac rfb - + 0% duty cy cle rsff s q qb r clk2 rdrp rcomp rdac 0.7v cout 1 2 vdac eaout scomp vdrp gateh2 gatel1 gateh1 csinp1 gatel2 vosns- csinp2 fb vout sense+ vout+ vout sense- vout- vin vin vdac - + x24.5 vdac - + x24.5 clk2 figure 2 ? pwm block diagram the rsff is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseco nds in response to a load step decrease. phases can overlap and go to 100% duty cycle in response to a load step incre ase with turn-on gated by the clock pulses. an error amplifier outpu t voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the voltage of the pwm ramp. this arrangement guar antees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. it also favors r esponse to a load step decrease which is appropriate given the low ou tput to input voltage ratio of most systems. the in ductor current will increase much more rapidly than decrease in respons e to load transients. this control method is designed to provide single cycle transient response where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. downloaded from: http:///
ir3092pbf page 12 of 37 09/07/05 figure 3 ? 2 phase oscillator and pwm waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; t slew = [l x (i max - i min )] / vout the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node voltage is then forced to decrease until conduction of the sy nchronous rectifiers body diode occurs. this increases the voltage acros s the inductor from vout to vout + v body diode . the minimum time required to reduce the current in the inductor in r esponse to a load transient decrease is now; t slew = [l x (i max - i min )] / (vout + v body diode ) since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as body braking and is accompl ished through the 0% duty cycle comparator. if the error amplifier s output voltage drops below 0.55v, this comparator turns off the low side gate driver. figure 4 depicts pwm operating waveforms under vari ous conditions clk1 clk2 50% internal oscillator ramp duty cycle ramp1 slope = 57mv / % dc 0.7v fixed ramp1 eaou t ramp2 ramp2 min duty cycle adjust ramp2 max duty cycle adjust the share adjust error amplifier can change the pulse width of ramp2 from 0.5x ramp1 to 2.0x ramp1 to force current sharing. downloaded from: http:///
ir3092pbf page 13 of 37 09/07/05 figure 4 ? pwm operating waveforms current sense amplifier a high speed differential current sense amplifier i s shown in figure 5. its gain decreases with increa sing temperature and is nominally 24.5 at 25oc and 20 at 125oc (-1400 pp m/oc). this reduction of gain tends to compensate t he 3850 ppm/oc increase in inductor dcr. since in most designs the ic junction is hotter than the inductors these two effects tend to cancel such that no additional temperature compensa tion of the load line is required. the current sense amplifier can accept positive dif ferential input up to 75mv and negative up to -20mv before clipping. the output of the current sense amplifier is summed with the dac voltage which is used for over curren t protection, voltage positioning and current sharing. figure 5 ? inductor current sensing and current sen se amplifier vcc under voltage lockout (uvlo) the vcc uvlo function monitors the vcc supply pin a nd ensures enough voltage is available to power the internal circuitry. during power-up the fault latch is reset when vcc exceeds 7.8v and all other faults are cle ared. the fault latch is set when vcc drops below 7.3v, resulting in 500m v of nominal vcc hysteresis for powering up into a load. 5vuvl under voltage lockout (5vuvl) the 5vuvl function is provided for converters using a separate voltage supply other than vcc for gate driver bias. the 5vuvl comparator prevents operation by discharging ss/del and forcing eaout low. the 5vuvl comparator has an ok threshold of 4.3v ensuring adequate gate drive v oltage is present and a fault threshold of 4.125v. clk1 pulse eaout 0.7v pwm ramp1 gateh1 gatel1 steady - state operation duty cycle increase due to load increase duty cycle decrease due to load decrease (body braking) or fault steady - state operation 0.6v c o l r l r s c s v o csa co i l v l v c downloaded from: http:///
ir3092pbf page 14 of 37 09/07/05 power good output the pwrgd pin is an open-collector output and shoul d be pulled up to a voltage source through a resist or. during soft start, the pwrgd remains low until the output volta ge is in regulation and ss/del is above 3.75v. the pwrgd pin becomes low if the fault latch is set. a high level at the pwrgd pin indicates that the converter is i n operation and has no fault, but does not ensure the output voltage is wi thin the specification. output voltage regulation w ithin the design limits can logically be assured however, assuming no compo nent failure in the system. tri-state gate drivers the gate drivers can deliver over 3.5a peak current . an adaptive non-overlap circuit monitors the volt age on the gatehx and gatelx pins to prevent mosfet shoot-through cur rent while minimizing body diode conduction. the error amplifier output of the control ic drives low in response to any fault condition such as vcc input under voltage or output overload. the 0% duty cycle comparator de tects this and drives both gate outputs low. this t ri-state operation prevents negative inductor current and negative out put voltage during power-down. the gate drivers revert to a high impedance off s tate at vccl and vcchx supply voltages below the no rmal operating range. an 80k ?uhvlvwrulvfrqqhfwhgdfurvvwkh*$7(;dqg3*1'; slqvwrsuhyhqwwkh*$7(;yrowdjhiurpulvlqjgxh to leakage or other cause under these conditions. over voltage protection (ovp) the output over-voltage protection comparator monit ors the output voltage through the fb pin, the posi tive remote sense point. if fb exceeds vdac plus 145mv (for vr 10.x, 480mv for opteron and athlon, selected with t he vid_sel pin), both gatel pins drive high and the ov p pin sources up to 10ma. the ovp circuit over-rid es the normal pwm operation and will fully turn-on the low side m osfet within approximately 150ns. the low side mosf et will remain on until the over-voltage condition ceases. the lower mosfets alone can not clamp the output vo ltage however an scr or n-mosfet could be triggered by the ovp pi n to prevent processor damage. error amplifier compensation can slow down the resp onse to an ovp condition if the voltage loop is too slow, which is usually not the case. the fb pin can only respond to an over-voltage condition once the eaout voltage has reached its minimum. until then, the fb pin is modified by the falling eaout voltage so fb is equal to vdac. the error amplifier compensation slew current generates a voltage acros s the rfb resistor that will mask the output voltag e ovp condition. again, for a typical fast voltage loop compensation scheme, a fairly large resistor is placed in serie s with the eaout to fb compensation capacitor to speed up the loop whic h results in no noticeable ovp sensing delay. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase convert er will be triggered thus providing effective prote ction without damage as long as all pcb traces and components are sized to handle the worst-case maximum current. if this is not possible, a fuse can be added in the input supply t o the multiphase converter. one scenario to be care ful of is where the input voltage to the multiphase converter may be pu lled below the level where the ics can provide adeq uate voltage to the low side mosfet thus defeating ovp. a body braking tm disable comparator has been included to prevent fa lse ovp firing during dynamic vid down changes. the bb disable comparator disables body braking tm when fb exceeds vdac by 80mv. the low side mosfet s will then be controlled to keep v(fb) and v(vout) within 80mv of v(vdac), below the 150mv intel ovp trip po int. downloaded from: http:///
ir3092pbf page 15 of 37 09/07/05 applications information figure 6 ? system diagram vid control the ir3092 provides three different microprocessor solutions. the vid_sel pin selects the appropriate digital-to-analog converters (dac), vid threshold voltages, and over voltage protection (ovp) threshold for vr10.x, opte ron, or athlon solutions. amd vid codes are shown in table 1; intel vid codes are found in table 2. the dac output voltage is available at the vdac pin. a detailed block dia gram of the vid control circuitry can be found in f igure 7. the vid pins are internally pulled up to 4.9v by 18ua current so urces. the vid input comparators have a 0.6v thresh old for vr10.x or 1.5v threshold for opteron and athlon. the selecte d dac voltage is provided at the error amplifier po sitive input and to the vdac pin by the trans-conductance dac bu ffer. the vdac voltage is trimmed to the error amplifier output voltage with eaout tied to fb via an accurat e resistor. this compensates dac buffer input offset, error amplifie r input offset, and errors in the generation of the fb bias current which is based on r rosc . this trim method provides 0.5% system accuracy. the ir3092 can accept changes in the vid code while operating and vary the vdac voltage accordingly. t he ic detects a vid change and blanks the dac output response for 400ns to verify the new code is valid and not due to skew or noise. the sink/source capability of the vdac buffer amp i s programmed by the same external resistor that set s the oscillator frequency, r rosc . the slew rate of the voltage at the vdac pin can be adjusted by an external capacitor between vdac pin and the vosns- pin. a resistor connected in ser ies with this capacitor is required to compensate t he vdac buffer amplifier. digital vid transitions result in a smoo th analog transition of the vdac voltage and conver ter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. vin vin 48ld mlpq ir3092 biasout csinm vid_sel csinp1 csinp2 eaout enable fb gateh1 gateh2 gatel1 gatel2 lgnd ocset ovp pgnd1 pgnd2 pwrgd rosc scomp setbias ss/del vcc vcch1 vcch2 vccl 5vuvl vdac vdrp vid0 vid1 vid2 vid3 vid4 vosns- vid5 nc nc nc nc nc nc nc nc nc nc nc nc vin rocset rfb rset cvcc cbias ccs2 rcs2 rcomp rcs1 ccs1 css rrosc cbst2 1 2 1 2 cout csc2 cin rdrp cdac ccomp rsc2 rdac cbst1 vout- vout+ powergood gndin vin vout sense- vout sense+ vid5 ovp enable vid0 vid1 vid2 vid3 vid4 csense- downloaded from: http:///
ir3092pbf page 16 of 37 09/07/05 "fast" vdac to fault 2.6v float voltage 60k shown default to vr10 with vid_sel grounded + - irosc dac buffer 4.9v 110k -+ 18ua 1.2v - + - + 1.5v 3.4v 0.6v vid0 vid1 vid2 vid3 vid4 vid_sel vid5 vdac vosns- h=athlon "slow" vdac dac defaults to vr10 with vid_sel grounded 5v 3.3v vid input comparators (1 of 6 shown) h=hammer vid=11111x fault blanking, 3.3us digital to analog converter athlon dac hammer dac figure 7? vid control block diagram vid = 11111x fault vid codes of 111111 and 111110 will set the fault l atch and disable the error amplifier. slew rate programming capacitor c dac and resistor r dac vdac sink current i sink and source current i source are determined by r rosc, and their value can be found using the curve in the typical operating characteristics. the slew rate of vdac down-slope sr down can be programmed by the external capacitor c dac as defined in equation (1) and shown in figure 6. r esistor r dac is used to compensate vdac circuit and is determined by equation (2). the slew rate of vdac up-slope sr up is proportional to the down-slope slew rate sr down and is given by equation (3). down sink dac sr i c (1) 2 15 10 2.3 5.0 dac dac c r (2) dac source up c i sr (3) downloaded from: http:///
ir3092pbf page 17 of 37 09/07/05 table 1a. amd opteron vid vid_sel open. v(vdac) is pre- positioned 50mv higher than vout values listed below for load positioning. vout is measured at eaout with rosc=42k and a 1690 ohm resistor connecting fb to eaout to cancel the 50mv pre-position offset. table 1b. amd athlon vid vidsel to vcc. v(vdac) is pre- positioned 50mv higher than vout values listed below for load positioning. vout is measured at eaout with rosc=42k and a 1690 ohm resistor connecting fb to eaout to cancel the 50mv pre-position offset. vid4 vid3 vid2 vid1 vid0 vout (v) vid4 vid3 vid2 vid1 vid0 vout (v) 0 0 0 0 0 1.550 0 0 0 0 0 1.850 0 0 0 0 1 1.525 0 0 0 0 1 1.825 0 0 0 1 0 1.500 0 0 0 1 0 1.800 0 0 0 1 1 1.475 0 0 0 1 1 1.775 0 0 1 0 0 1.450 0 0 1 0 0 1.750 0 0 1 0 1 1.425 0 0 1 0 1 1.725 0 0 1 1 0 1.400 0 0 1 1 0 1.700 0 0 1 1 1 1.375 0 0 1 1 1 1.675 0 1 0 0 0 1.350 0 1 0 0 0 1.650 0 1 0 0 1 1.325 0 1 0 0 1 1.625 0 1 0 1 0 1.300 0 1 0 1 0 1.600 0 1 0 1 1 1.275 0 1 0 1 1 1.575 0 1 1 0 0 1.250 0 1 1 0 0 1.550 0 1 1 0 1 1.225 0 1 1 0 1 1.525 0 1 1 1 0 1.200 0 1 1 1 0 1.500 0 1 1 1 1 1.175 0 1 1 1 1 1.475 1 0 0 0 0 1.150 1 0 0 0 0 1.450 1 0 0 0 1 1.125 1 0 0 0 1 1.425 1 0 0 1 0 1.100 1 0 0 1 0 1.400 1 0 0 1 1 1.075 1 0 0 1 1 1.375 1 0 1 0 0 1.050 1 0 1 0 0 1.350 1 0 1 0 1 1.025 1 0 1 0 1 1.325 1 0 1 1 0 1.000 1 0 1 1 0 1.300 1 0 1 1 1 0.975 1 0 1 1 1 1.275 1 1 0 0 0 0.950 1 1 0 0 0 1.250 1 1 0 0 1 0.925 1 1 0 0 1 1.225 1 1 0 1 0 0.900 1 1 0 1 0 1.200 1 1 0 1 1 0.875 1 1 0 1 1 1.175 1 1 1 0 0 0.850 1 1 1 0 0 1.150 1 1 1 0 1 0.825 1 1 1 0 1 1.125 1 1 1 1 0 0.800 1 1 1 1 0 1.100 1 1 1 1 1 off 4 1 1 1 1 1 off 4 note: 4 output disabled (fault mode) downloaded from: http:///
ir3092pbf page 18 of 37 09/07/05 table 2. intel vr10.x vid (vid_sel grounded, measur ed at eaout=fb. ) processor pins (0 = low, 1 = high) processor pins (0 = low, 1 = high) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) 0 1 0 1 0 0 0.8375 1 1 0 1 0 0 1.2125 0 1 0 0 1 1 0.8500 1 1 0 0 1 1 1.2250 0 1 0 0 1 0 0.8625 1 1 0 0 1 0 1.2375 0 1 0 0 0 1 0.8750 1 1 0 0 0 1 1.2500 0 1 0 0 0 0 0.8875 1 1 0 0 0 0 1.2625 0 0 1 1 1 1 0.9000 1 0 1 1 1 1 1.2750 0 0 1 1 1 0 0.9125 1 0 1 1 1 0 1.2875 0 0 1 1 0 1 0.9250 1 0 1 1 0 1 1.3000 0 0 1 1 0 0 0.9375 1 0 1 1 0 0 1.3125 0 0 1 0 1 1 0.9500 1 0 1 0 1 1 1.3250 0 0 1 0 1 0 0.9625 1 0 1 0 1 0 1.3375 0 0 1 0 0 1 0.9750 1 0 1 0 0 1 1.3500 0 0 1 0 0 0 0.9875 1 0 1 0 0 0 1.3625 0 0 0 1 1 1 1.0000 1 0 0 1 1 1 1.3750 0 0 0 1 1 0 1.0125 1 0 0 1 1 0 1.3875 0 0 0 1 0 1 1.0250 1 0 0 1 0 1 1.4000 0 0 0 1 0 0 1.0375 1 0 0 1 0 0 1.4125 0 0 0 0 1 1 1.0500 1 0 0 0 1 1 1.4250 0 0 0 0 1 0 1.0625 1 0 0 0 1 0 1.4375 0 0 0 0 0 1 1.0750 1 0 0 0 0 1 1.4500 0 0 0 0 0 0 1.0875 1 0 0 0 0 0 1.4625 1 1 1 1 1 1 off 4 0 1 1 1 1 1 1.4750 1 1 1 1 1 0 off 4 0 1 1 1 1 0 1.4875 1 1 1 1 0 1 1.1000 0 1 1 1 0 1 1.5000 1 1 1 1 0 0 1.1125 0 1 1 1 0 0 1.5125 1 1 1 0 1 1 1.1250 0 1 1 0 1 1 1.5250 1 1 1 0 1 0 1.1375 0 1 1 0 1 0 1.5375 1 1 1 0 0 1 1.1500 0 1 1 0 0 1 1.5500 1 1 1 0 0 0 1.1625 0 1 1 0 0 0 1.5625 1 1 0 1 1 1 1.1750 0 1 0 1 1 1 1.5750 1 1 0 1 1 0 1.1875 0 1 0 1 1 0 1.5875 1 1 0 1 0 1 1.2000 0 1 0 1 0 1 1.6000 note: 4. output disabled (fault mode) oscillator resistor r rosc the oscillator frequency is programmable from 100kh z to 540khz with an external resistor r rosc as shown in figure 6. the oscillator generates an internal 50% duty cycle saw tooth signal (figure 4.) that is used to gener ate 180 out-of-phase timing pulses to set phase 1 and 2 rs flip-flops. once the switching frequency is chosen, r rosc can be determined from the curve in the i(setbias) vs. rosc curve in the t ypical operating characteristics section. soft start, over-current fault delay, and hiccup mo de the ir3092 has a programmable soft-start function t o limit the surge current during converter power-up . a capacitor connected between the ss/del and lgnd pins controls soft start timing as well as over-current protecti on delay and hiccup mode timing. figure 8 depicts the various operating modes of the ss/del function. under a no fault condition, the s s/del capacitor will charge. the ss/del charge soft-start duration is controlled by a 55ua charge current which charge s css up to 4.0v. the error amplifier output is clamped low until ss/ del reaches 1.3v. the error amplifier will then reg ulate the converters output voltage to match the ss/del volt age less the 1.3v offset until it reaches the level determined by the vid inputs. the pwrgd signal is asserted once the s s/del voltage exceeds 3.75v. downloaded from: http:///
ir3092pbf page 19 of 37 09/07/05 vcc and 5vuvl under voltage lock outs, a vid=11111x fault, or low enable pin immediately set the fault latch causing ss/del to begin discharging. the hiccup duration is controlled by a 5.5ua discharge current until the discharge comparator threshold of 0.26v is reached. if the f ault has cleared, the fault latch will reset allowi ng a normal soft-start to occur. a delay is included if an over-current condition oc curs after a successful soft start sequence. this i s required since over- current conditions can occur as part of normal oper ation due to load transients or vid transitions. if an over-current fault occurs during normal operation, the over current co mparator will initiate the discharge of the capacit or at ss/del but will not set the fault latch immediately. if the ov er-current condition persists long enough for the s s/del capacitor to discharge below the 3.75v threshold of the delay co mparator, the fault latch will be set pulling the e rror amplifiers output low, inhibiting switching and de-asserting the pwrg d signal. an additional discharge current is introd uced during an over current condition. the 5.5ua discharge current res ults in a long delay duration where ss/del discharg es from its 4v peak to the 3.75v fault delay threshold. this pote ntially long over-current protection activation del ay could result in potential power stage damage therefore an additiona l 45ua discharge current source assists the 5.5ua d ischarge current if an over current condition is occurring and the s s/del capacitor is above 3.75v. 30mv of hysteresis is included in the delay comparator to prevent pwrgd chatter when ss/d el is at the delay threshold. the ss/del capacitor will continue to discharge unt il it reaches 0.26v where the fault latch is reset allowing a normal soft start to occur. if an over-current condition is ag ain encountered during the soft start cycle, the fa ult latch will be set without any delay and hiccup mode will begin. durin g hiccup mode the 10 to 1 charge to discharge ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. the converter can be disabled if the ss/del pin is pulled below 0.9v. figure 8 ? operating waveforms vcc start - up normal operation hiccup over - current protection re - start after ocp clears power - down 7.6v u vlo (12v) 5vuvl 4.3v ss/del 3.75v pwrgd vout iout (5vuvl gates fault mode) (vcc gates fault mode) 1.3v (vout changes due to load and vid changes) ocp delay ocp threshold downloaded from: http:///
ir3092pbf page 20 of 37 09/07/05 soft-start delay time t ssdel is the time to charge ss/del up to 1.3v. after this the error amplifier o utput is released to allow the soft start. the soft start time t ss represents the time during which converter voltage rises from zero to v o. t ss can be programmed by c ss using equation (4). o ss o ss chg ss v t v t i c * 10 * 55 * 6 ? (4) once c ss is chosen, the soft start delay time t ssdel, the over-current fault latch delay time t ocdel , and the delay time t vccpg from output voltage (v o ) in regulation to power good are fixed and shown i n equation (5), (6) and (7) respectively. 6 10 * 55 3.1* * ? ' ss chg ss ssdel c i v c t (5) 6 10 *5.50 25.0* * ? ' ss dischg ss ocdel c i v c t (6) 6 10 * 55 )3.1 75.3(* * ? ' o ss chg ss vccpg v c i v c t (7) over current protection (ocp) the current limit threshold is set by a resistor co nnected between the ocset and vdac pins. if the ave rage current sense amplifier output plus vdac voltage exceeds th e ocset voltage, the over-current protection is tri ggered. a delay is included if an over-current condition oc curs after a successful soft-start sequence. this i s required since over- current conditions can occur as part of normal oper ation due to load transients or vid transitions. if an over-current fault occurs during normal operation, the over current co mparator will initiate the discharge of the capacit or at ss/del but will not set the fault latch immediately. if the ov er-current condition persists long enough for the s s/del capacitor to discharge below the 250mv offset of the delay compa rator, the fault latch will be set pulling the erro r amplifiers output low inhibiting switching in the phase ics and de-as serting the pwrgd signal. see soft start, over-cur rent fault delay, and hiccup mode. the inductor dc resistance r l is utilized to sense the inductor current. i limit is the required over current limit. i ocset, the bias current of ocset pin, is set by r rosc and is also determined by the curve in the typical operating characteristics. r ocset is defined in the following equation (8). ocset l limit ocset i r fsw vin l vo vin vo i r /5.23 ) * 2 ) ( 2 ( (8) downloaded from: http:///
ir3092pbf page 21 of 37 09/07/05 adaptive voltage positioning adaptive voltage positioning is needed to reduce ou tput voltage deviations during load transients and power dissipation of the load when it is drawing maximum current. the ci rcuitry related to voltage positioning is shown in figure 9. resistor r fb is connected between the error amplifiers inverti ng input pin fb and the converters output voltage. an internal current source whose value is programmed by the sam e external resistor that programs the oscillator fr equency, r rosc , pumps current out of the fb pin. the fb bias curren t develops a positioning voltage drop across r fb which forces the converters output voltage lower to v(vdac)-i(fb)* r fb to maintain a balance at the error amplifier input s. r fb is selected to program the desired amount of fixed off set voltage below the dac voltage. the voltage at the vdrp pin is an average of both p hase current sense amplifiers and represents the su m of the vdac voltage and the average inductor current of all the phases. the vdrp pin is connected to the fb pin th rough the resistor. the error amplifier forces the voltage on the fb pi n to equal vdac through the power supply loop there fore the current through rdrp is equal to (vdrp-vdac) / r drp. as the load current increases, the vdrp voltage i ncreases accordingly which results in an increase r fb current, further positioning the output regulated v oltage lower thus making the output voltage reduction proportional to an increase in lo ad current. the droop impedance or output impedance of the converter can thus be programmed by the resistor r drp. the offset and slope of the converter output impe dance are independent of the vdac voltage. amd specifies the acceptable power supply regulatio n window as 50mv around their specified vid tables . vr10.x specifies the vid table voltages as the absolute ma ximum power supply voltage. in order to have all t hree dac options, the opteron and athlon dac output voltages are pre- positioned 50mv higher than listed in amd specs. d uring testing, a series resistor is placed between eaout and fb to cancel the additional 50mv out of the dac . the fb bias current, equal to irosc, develops the 50mv cancella tion voltage. trimming the vdac voltage by monitor ing v(eaout) with this 50mv cancellation resistor in circuit als o trims out errors in the fb bias current. the vdrp pin voltage represents the average current of the converter plus the dac voltage. the load cu rrent can be retrieved by subtracting the vdac voltage from the vdrp voltage. csinm3 csinm2 - v(csavg) + vdrp buffer irosc + vpositioning - idrp rdrp cdac - + error amplifier -+ rcomp vdac ccomp rdac rfb irosc vdac vdrp vosns- fb vout sense+ eaout vout sense- csinp2 vdac - + x24.5 csinp3 vdac - + x24.5 figure 9 - adaptive voltage positioning downloaded from: http:///
ir3092pbf page 22 of 37 09/07/05 a resistor r fb between fb pin and the converter output is used to create output voltage offset v o_nlofst which is the difference between v dac voltage and output voltage at no load condition. a n internal current source whose value is programmed by the same external resistor that progr ams the oscillator frequency, r rosc , pumps current i rosc out of the fb pin. the voltage at the vdrp pin is an average of both p hase current sense amplifiers and represents the su m of the vdac voltage and the average inductor current of all the phases. the vdrp pin is connected to the fb pin th rough the adaptive voltage positioning resistor r drp. adaptive voltage positioning lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. r fb and r drp are determined by (9) and (10) respectively, where r o is the required output impedance of the converter. rosc nlofst o fb i v r _ (9) o l fb drp r r r r 2 5.23 (10) lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor. the equ ation of the sensing network is, s s l l s s l c c sr sl r s i c sr s v s v 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr. if the two time constants match, the voltage across ccs is proportional to the current through l, and the s ense circuit can be treated as if only a sense resi stor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch currents. t he output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in s eries with the inductor, this is the only sense method that can su pport a single cycle transient response. other meth ods provide no information during either load increase (low side s ensing) or load decrease (high side sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in m any ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and th e output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and ou tput voltage are all additional sources of peak-to- average errors. the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the vo ltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different from that of the rea l inductor current. the time constant mismatch does not affect the average current sharing among the multiple phases, but affects the ac component of the inductor curren t as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. downloaded from: http:///
ir3092pbf page 23 of 37 09/07/05 measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c r l r (11) the bias current flowing out of the non-inverting i nput of the current sense amplifier creates a volta ge drop across r cs, which is equivalent to an input offset voltage of t he current sense amplifier. the offset affects the accuracy of converter current signal ishare as well as the accuracy of th e converter output voltage if adaptive voltage posi tioning is adopted. to reduce the offset voltage, a resistor r cso should be added between the amplifier inverting inp ut and the converter output, as shown in fig1 . the resistor r cso is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. cs csin csin cso r i i r ? ? (12) if r cso is not used, r cs should be chosen so that the offset voltage is sma ll enough. usually r cs should be less than 2 k ?dqgwkhuhiruhdodujhu& cs value is needed. inductor dcr temperature correction if the current sense amplifier temperature dependen t gain is not adequate to compensate the inductor d cr tc, a negative temperature coefficient (ntc) thermistor c an be added. the thermistor should be placed close to the inductor and connected in parallel with the feedback resisto r, as shown in figure 10. the resistor in series wi th the thermistor is used to reduce the nonlinearity of the thermistor. figure 10- temperature compensation of inductor dcr remote voltage sensing to compensate for impedance in the ground plane, th e vosns- pin is used for remote sensing and connect s directly to the load. the vdac voltage is referenced to vosns- to avoid additional error terms or delay related to a separate differential amplifier. the capacitor connecting th e vdac and vosns- pins ensure that high speed trans ients are fed directly into the error amplifier without delay. master-slave current share loop current sharing between phases of the converter is achieved by a master-slave current share loop topol ogy. the output of the phase 1 current sense amplifier sets the ref erence for the share adjust error amplifier. the s hare adjust error amplifier will then adjust the duty cycle of pwm ra mp2 to force its input error to zero, resulting in accurate current sharing. vdrp buffer irosc - + error amplifier -+ vdac rfb rdrp vdac eaout vdrp vosns- fb vout sense+ current + vdac rlinear rntc downloaded from: http:///
ir3092pbf page 24 of 37 09/07/05 the maximum and minimum duty cycle adjust range of ramp2 compared to ramp1 has been limited to 0.5x an d 2.0x of the masters ramp (see figure 3.). the crossover fr equency of the current share loop can be programmed with a capacitor at the scomp pin so that the share loop does not in teract with the output voltage loop. a 22nf capacit or from scomp to lgnd is good for most of the applications. if neces sary have a 1k resistor in series with the csc to make t he current loop a little bit faster. the scomp capacitor is driven by a trans-conductanc e stage capable of sourcing and sinking 25ua. the duty cycle of ramp2 inversely tracks the voltage on the scomp pin ; if v(scomp) increases, ramp2s slope will increas e and the effective duty cycle will decrease resulting in a r eduction in phase 2s output current. due to the l imited 25ua source current, an scomp pre-charge circuit has been inclu ded to pre-condition v(scomp) so that the duty cycl e of ramp2 is equal to ramp1 prior to any gatehx high pulses. t he pre-condition circuit can source 400ua. the equ al duty cycle comparator (see block diagram) activates a pre-char ge circuit when ss/del is less than 0.7v. the erro r amplifier becomes active enabling gateh switching when ss/del is above 1.3v. compensation of voltage loop the adaptive voltage positioning is used in the com puter applications to meet the load line requiremen ts. like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and spli ts the double poles of the power stage, which make the voltage loop compen sation much easier. resistors r fb and r drp are chosen according to equations (9) and (10), an d the selection of compensation types depends on the capacitors used. for the application s using electrolytic, polymer or al-polymer capacit ors, type ii compensation shown in figure 11 (a) is usually enou gh. while for the applications with only low esr ce ramic capacitors, type iii compensation shown in figure 11 (b) is pre ferred. (a) type ii compensation (b) type iii compensation figure11 . voltage loop compensation network type ii compensation determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the ind uctor, the crossover frequency of the voltage loop can be estimated by equations (13), where c e and r ce are the equivalent capacitance and esr of output c apacitors respectively and r le is the equivalent resistance of inductor dcr. ) * ( * 2 ce le fb cs e drp c r r r g c r f s (13) cfb cdrp rcomp eaout ccp1 ccomp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 rcomp ccp1 eaout ccomp rfb rdrp vo+ vdrp vdac + - eaout fb fb downloaded from: http:///
ir3092pbf page 25 of 37 09/07/05 r comp and c comp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequenc y and transient load response. choose the desired cro ssover frequency fc1 around fc estimated by equatio n (13) and determine r comp and c comp. m in fb e e c comp f v r c l f r 2 1 ) 2( s (14) comp e e comp r c l c 10 (15) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. in equation (14), v in is the input voltage, f m is the pwm comparator gain (refer to equation (22)). type iii compensation determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the ind uctor, the crossover frequency of the voltage loop can be estimated by equations (16). le fb cs e drp c r r g c r f * * 2 s (16) choose the desired crossover frequency fc1 around f c estimated by equation (16). select other componen ts to ensure the slope of close loop gain is -20db/dec around the cr ossover frequency. choose resistor r fb1 according to equation (17), and determine c fb and c drp from equations (18) and (19). fb fb r r 2 1 1 to fb fb r r 3 2 1 (17) 1 1 4 1 fb c fb r f c s (18) drp fb fb fb drp r c r r c ) ( 1 (19) r comp and c comp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequenc y and transient load response. determine r comp and c comp from equations (20) and (21), where f m is the pwm comparator gain defined by equation (22). m i fb e e c comp f v r c l f r 2 1 ) 2( s (20) comp e e comp r c l c 10 (21) downloaded from: http:///
ir3092pbf page 26 of 37 09/07/05 ramp i o m v v v f * (22) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. set biasout voltage resistor rset biasout pin provides 150ma open-looped regulated vo ltage for gate drive bias, and the voltage is set b y setbias through an external resistor rset connecting betwee n setbias pin and ground. bias current i setbias is a function of rosc. rset is chosen by equation (23) setbias biasout set i v r (23) downloaded from: http:///
ir3092pbf page 27 of 37 09/07/05 design example ir3092 demo board rev.2 for vrd10.0 fmb1.5 input voltage: v i =12 v dac voltage: v dac =1.35 v no load output voltage offset: v o_nlofst =25 mv output current: i o =80 a dc output current limit set point: i limit =100 a output impedance: r o =1.3 m ? vcc ready to vcc power good delay: t vccpg =0-10ms soft start time: t ss =2 ms dynamic vid down-slope slew rate: sr down =2.5mv/us control ic: ir3092 phase number: n=2 switching frequency: f sw =180 khz output inductor(per phase): l=0.45 uh, r l =0.7 m ? (1m ? when winding temperatures around 120c) output capacitors: c e =0.011f, r ce =1 m ? once the switching frequency is chosen, r osc can be determined from the curve in this datasheet . for switching frequency of 180 khz per phase, choose r osc =47.5k ? calculate the soft start capacitor from the require d soft start time 6ms. f v t i c o ss chg ss 8 3 3 6 10 *3.8 10 * 25 35.1 10 *2* 10 * 55 * ? ? ? ? choose c ss = 0.1 uf with the selected css value, we can calculate the f ollowing delay times: the over-current fault latch delay time t ocdel will be: ms i v c t dischg ss ocdel 5.0 10 *5.50 25.0* 10 *1.0 * 6 6 ' ? ? specifications: power stage design external components oscillator resistor rosc soft start capacitor c ss downloaded from: http:///
ir3092pbf page 28 of 37 09/07/05 the soft start delay time is ms i v c t chg ss ssdel 3.2 10 * 55 3.1* 10 *1.0 * 6 6 ' ? ? the power good delay time is ms v i v c t o chg ss vccpg 0.2 10 * 55 )3.1 75.3(* 10 *1.0 * 6 6 ' ? ? from this data sheet, the sink current i sink of vdac pin corresponding to r osc =47.5k ? lv x$ calculate the vdac down-slope slew-rate programming capacitor from the required down-slope slew rate. nf sr i c down sink vdac 20 10/ 10 5.2 10 50 6 3 6 ? ? ? choose c vdac =22nf calculate the programming resistor. ? ? ? 2 9 15 2 15 10 * 22 10 *2.3 5.0 10 2.3 5.0 dac dac c r 7.1 ? in practice slightly adjust r dac to get desired slew rate. the source current of vdac pin is 55ua, and the vda c up-slope slew rate is us mv c i sr vdac source up / 5.2 10 22 10 55 9 6 ? ? according to the spec, the output current limit set point i limit = 100a. the bias current i ocset set by r rosc is around 26ua. use equation (10) to calculate the value of r ocset: 6 3 3 6 10 * 26 5.23 * 10 *1 *) 10 * 180 * 12 * 10 * 45.0*2 ) 325 .1 12(* 325 .1 2 100 ( /5.23 ) * 2 ) ( 2 ( ? ? ? ocset l limit ocset i r fsw vin l vo vin vo i r = 52 k ?&krrvh 5 ocset =52.3k ? no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp the value of the internal current source current i rosc (i fb in this datasheet curve) is 26ua according to r rosc = 47.5k ? vdac slew rate programming capacitor c dac and resistor r dac over current setting resistor r ocset downloaded from: http:///
ir3092pbf page 29 of 37 09/07/05 ? ? 6 3 _ 10 * 26 10 * 25 rosc nlofst o fb i v r 961 ?&krrvh5 fb = 1k ? : ? ? k r r r r o l fb drp 4.9 10 *3.1*2 5.23 * 10 *1* 10 *1 2 5.23 3 3 3 choose r drp = 9.53k ? inductor current sensing capacitor c cs and resistors r cs and r cso choose capacitor c cs = 0.22uf calculate r cs : ? ? ? k c r l r cs l cs 9.2 10 * 22.0 10 *7.0/ 10 * 45.0 6 3 6 choose r cs =3k ? the bias currents of csin+ and csin- are 0.2ua and 0.4ua respectively. calculate resistor r cso , : : ?? k k r i i r cs csin csin cso 5.1 3* 4.0 2.0 set biasout voltage resistor rset bias current i setbias is around 95ua in this case. set v biasout around 8v to be gate drive voltage of mosfets. : ? k i v r setbias biasout set 21.84 10 * 95 8 6 choose r set =82.5k ? al-polymer output capacitors are used in the design , and the crossover frequency of the voltage loop c an be estimated as, khz r r r g c r f ce le fb cs e drp c 17 ] 10 *1 )2/ 10 *7.0( 10 *1 5.23[ 011 .0 2 10 * 53.9 ) ( 2 3 3 3 3 ? ? s s r comp and c comp are used to fine tune the crossover frequency and transient load response. choose the desired crossover frequency fc1 (=25khz) and de termine r comp and c comp . 175 .0 63.0 12 325 .1 ramp i o m v v v f : ? k f v r c l f r m i fb e e c comp 30 175 .0 12 10 *1 011 .0 )2/ 10 450 ( ) 10 25 2( ) 2( 3 9 23 2 1 s s nf r c l c comp e e comp 17 10 30 011 .0 )2/ 10 450 ( 10 10 3 9 ? in practice, adjust r comp and c comp if need to get desired dynamic load response perfor mance. compensation of voltage loop downloaded from: http:///
ir3092pbf page 30 of 37 09/07/05 mathcad file to estimate the power dissipation of t he ic initial conditions: no.of phases: n 2 icq 29 ma ( ) ic supply voltage: vcc 12 v( ) , ic supply current(quiescent): total high side driver vcch supply current(quiescen t): iqh 5 n ? ma ( ) total low side driver vccl supply current(quiescent ): iql 5 n ? ma ( ) biasout voltage: vbias 7.5 v( ) switching frequency per phase: fsw 200 khz ( ) thermal impedance of ic: t ja 27 ( o c/w) the data from the selected mosfets: control fet ir3715z, number of control fet per phas e: nc 2 control fet total gate charge: qgc 11 nc( ) synchronous fet ir3717, number of sync. fet per pha se: ns 2 sync fet total gate charge: qgs 33 nc( ) the ic will have less power dissipation if using ex ternal gate driver supply. for the worst case estim ation, assume using the bias regulator for all the gate dr ive supply voltage. 1. quiescent power dissipation total quiescent power dissipation: pq icq iqh iql ( ) vcc ? 10 3 ? ? pq 0.588 w( ) 2. the power loss to drive the gate of the mosfets with the assumption of the low mosfet gate resistan ces, most gate drive losses are dissipated in the driver circuit. pdrv vbias fsw ? 10 3 ? n ? nc qgc ? ns qgs ? ( ) 10 9 ? a ? o ? ? pdrv 0.264 w( ) where the ig fsw 10 3 ? n ? nc qgc ? ns qgs ? ( ) ? 10 9 ? ? term in the equation gives the total average bias current required to drive all the mosfets. 3. the bias regulator power loss to supply driving the mosfets preg vcc vbias ( ) ig ? preg 0.158 w( ) 4. total power dissipation of the ic: pdiss pq pdrv preg pdiss 1.01 w( ) and the total junction temperature rising is: pdiss t ja ? 27.281 ( o c) downloaded from: http:///
ir3092pbf page 31 of 37 09/07/05 1 2 48ld mlpq ir3092 biasout csinm vid_sel csinp1 csinp2 eaout enable fb gateh1 gateh2 gatel1 gatel2 lgnd ocset ovp pgnd1 pgnd2 pwrgd rosc scomp setbias ss/del vcc vcch1 vcch2 vccl 5vuvl vdac vdrp vid0 vid1 vid2 vid3 vid4 vosns- vid5 nc nc nc nc nc nc nc nc nc nc nc nc 1 2 powergood enable 12vin vreturn vcore vid5 ovp vid3 vid4 vid1 vid2 12vin vid0 12vin 1 2 1 1 2 48ld mlpq ir3092 biasout csinm vid_sel csinp1 csinp2 eaout enable fb gateh1 gateh2 gatel1 gatel2 lgnd ocset ovp pgnd1 pgnd2 pwrgd rosc scomp setbias ss/del vcc vcch1 vcch2 vccl 5vuvl vdac vdrp vid0 vid1 vid2 vid3 vid4 vosns- vid5 nc nc nc nc nc nc nc nc nc nc nc nc powergood 12vin enable vcore vreturn ovp vid3 vid5 vid4 vid0 vid2 5vin vid1 5vin 5vin 12vin figure 13. 12v control, 5v power, vr10.0 converter figure 12. 12v control, 12v power opteron converter downloaded from: http:///
ir3092pbf page 32 of 37 09/07/05 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coup led to the ic. refer to the schematic in figure 6 C system diagram. x dedicate at least one inner layer of the pcb as po wer ground plane (pgnd). x the center pad of ic must be connected to ground p lane (pgnd) using the recommended via pattern shown in pcb and stencil design methodology . x the ics pgnd1, 2 and lgnd should connect to the c enter pad under ic. x the following components must be grounded directly to the lgnd pin on the ic using a ground plane on the component side of pcb: css, rsc2, rset , and cvcc. the lgnd should only be connected to ground plane on the center pad under i c x place the decoupling capacitors cvcc and cbias as close as possible to the vcc and vccl pins. the ground side of cbias should not be connec ted to lgnd and it should directly be grounded through vias. x the following components should be placed as close as possible to the respective pins on the ic: rrosc, rocset, cdac, rdac, css, csc2, rsc2, cco mp rcomp and rset. x place current sense capacitors ccs1, 2 and resisto rs rcs1, 2 as close as possible to csinp1, 2 pins of ic and route the two current sense signal s in pairs connecting to the ic. the current sense signals should be located away from gate driv e signals and switch nodes. x use kelvin connections to route the current sense traces to each individual phase inductor, in order to achieve good current share between phases. x place the input decoupling capacitors closer to th e drain of top mosfet and the source of the bottom mosfet. if possible, use multiple smaller va lue ceramic caps instead of one big cap, or use low inductance type of ceramic cap, to reduce t he parasitic inductance. x route the high current paths using wide and short traces or polygons. use multiple vias for connections between layers. x the symmetry of the following connections from pha se to phase is important for proper operation: - the kelvin connections of the current sense signa ls to inductors. - the gate drive signals from the ic to the mosfets . - the polygon shape of switching nodes. downloaded from: http:///
ir3092pbf page 33 of 37 09/07/05 pcb and stencil design methodology x 7x7 x 48 lead x 0.5mm pitch mlpq see figures 14-16. pcb metal design (0.5mm pitch leads) 1. lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be ?ppwrplqlpl]hvkruwlqj 2. lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension e nsures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. 3. center pad land length and width should be = max imum part pad length and width. however, the minimum metal to metal spacing should be ?ppr]&rsshu?ppirur]&rsshu and ?ppirur]&rsshu 4. sixteen 0.30mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic, a nd to transfer heat to the pcb. pcb solder resist design (0.5mm pitch leads) 1. lead lands. the solder resist should be pulled away from the metal lead lands by a minimum of 0.060mm. the solder resist mis-alignment is a maxi mum of 0.050mm and it is recommended that the lead lands are all nsmd. therefore pullin g the s/r 0.060mm will always ensure nsmd pads. 2. the minimum solder resist width is 0.13mm, there fore it is recommended that the solder resist is completely removed from between the lead lands form ing a single opening for each group of lead lands. 3. at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ?ppuhpdlqv 4. land pad. the land pad should be smd, with a mi nimum overlap of the solder resist onto the copper of 0.060mm to accommodate solder resist mis- alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. 5. ensure that the solder resist in-between the lea d lands and the pad land is ?ppgxhwrwkh high aspect ratio of the solder resist strip separa ting the lead lands from the pad land. 6. the single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. stencil design (0.5mm pitch leads) 1. the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited wil l minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0. 25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wid e are difficult to maintain repeatable solder release. 2. the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. 3. the center land pad aperture should be striped w ith 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the cen ter pad. if too much solder is deposited on the center land pad the part will float and the lea d lands will be open. 4. the maximum length and width of the center land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull b ack to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3092pbf page 34 of 37 09/07/05 figure 14. pcb metal and solder resist. downloaded from: http:///
ir3092pbf page 35 of 37 09/07/05 figure 15. pcb metal and component placement. downloaded from: http:///
ir3092pbf page 36 of 37 09/07/05 figure 16. stencil design. downloaded from: http:///
ir3092pbf page 37 of 37 09/07/05 package dimensions data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on irs web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on www.irf.com downloaded from: http:///

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